Ball grid array semiconductor package and method of fabricating the same
US6818538B2 · kind B2 · utility
4Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Apr 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A ball grid array semiconductor packaging technology is provided, which is characterized in that openings of a solder mask are formed on a given edge of a die attachment area, and entire or partial width of each opening is disposed outside the die attachment area. Accordingly, air within the opening of the solder mask is sufficiently eliminated during die bonding process, so as to prevent void formation as adhesive is filled into the opening. Therefore, in the follow-up steps, high temperature in reflowing process will not cause popcorn as in the prior-art, so as to remain good quality of the semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.