Etching process for high-k gate dielectrics
US6818553B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Jun 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a gate electrode comprising the following steps. A substrate having a high-k gate dielectric layer formed thereover is provided. A gate layer is formed over the high-k gate dielectric layer. A gate ARC layer is formed over the gate layer. The gate ARC layer and the gate layer are patterned to form a pattern gate ARC layer and a patterned gate layer. The high-k gate dielectric layer not under the patterned gate layer is partially etched and a smooth exposed upper surface of the patterned gate layer is formed. The partially etched high-k gate dielectric layer portions not under the patterned gate layer are removed to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.