Method of fabricating annealed wafer
US6818569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Jan 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an annealed wafer of high quality by forming a defect-free active region of a device and controlling an irregular resistivity characteristic. The method includes a first annealing step of pre-heating a silicon wafer at a temperature of about 500° C. in a furnace in an ambience of a gas selected from the group consisting of Ar, N2 and an inert gas including Ar and N2; a second annealing step of changing the ambience of the gas into a 100% H2 gas ambience, increasing the temperature to 850° C.-1,150° C., and carrying out annealing for about an hour by maintaining the increased temperature; a third annealing step of changing the ambience of the gas into a 100% Ar gas ambience, increasing the temperature to about 1,200° C., and carrying out annealing for about an hour while the temperature of about 1,200° C. is maintained; and a temperature dropping step of decreasing the temperature in the furnace below about 500° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.