Chip design with power rails under transistors
US6818931B2 · kind B2 · utility
11Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Jun 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and an integrated circuit having power rails under transistors. In a preferred embodiment, power rails are formed over a substrate. Devices, such as FET transistors, are formed over the power rails. A preferred device is an inverter. The method comprises forming a first power rail (VSS) over the substrate. Then forming a second power rail (e.g., VDD) over the first power rail. The second power rail is insulated from the first power rail. Next, transistors are formed over the first and the second power rails.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.