Vertical compound semiconductor field effect transistor structure
US6818939B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Jul 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/831
Abstract
In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84, 85, 87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.