Jitter estimation for a phase locked loop
US6819192B2 · kind B2 · utility
6Cited by
4References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Feb 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for estimating jitter in a phase locked loop is provided. The estimation is determined from a simulation that uses a representative power supply waveform having noise as an input. Further, a computer system for estimating jitter in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to estimate jitter in a phase locked loop is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.