Method and circuit for eliminating glitches in a disk drive read head
US6819515B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 2000 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Jan 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2005/0018
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved bias circuit for a disk drive head which reduces or eliminates transients while switching biasing. Embodiments of the invention are directed to eliminating transients while switching the bias of a MR head such as from current bias to voltage biasing. In an embodiment of the present invention, bias enable signals from a control circuit are inputs to delay circuits. The delay circuits provide a delay on the high-to-low transition, and essentially no delay on the low-to-high transition. The unsymmetrical delay ensures that the read head bias current will continue to be driven during the biasing transition to reduce voltage swings that could damage the head.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.