Programmable reference for 1T/1C ferroelectric memories
US6819601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Jun 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.