Apparatus and method for a sense amplifier circuit that samples and holds a reference voltage
US6819612B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Mar 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit. Specifically, a sample and hold sense amplifier circuit that is capable of sampling and holding a reference voltage comprises a reference voltage sampler circuit coupled to a cross-coupled inverter latch. The reference voltage sampler circuit is coupled to a bitline associated with a memory cell. The reference voltage is sampled from a precharge voltage taken off the bitline, and is used to read a state on a memory cell. The cross-coupled inverter latch is also coupled to the bitline, and is used for amplifying a voltage difference between an output voltage from the cross-coupled inverter latch and the reference voltage. The output voltage is based on a static bitline voltage from the bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.