Method and apparatus for standby power reduction in semiconductor devices
US6819621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Dec 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to a local supply node, which during standby conditions when the word line driver circuit is not driving a word line, is maintained at a voltage less than that of a global power supply node. In one embodiment, the local power supply node is coupled to the global power supply node by means of at least one decoupling transistor receiving a control signal at its gate and by a vt-connected transistor, such that the voltage on the local power supply node is maintained at a level not exceeding one transistor threshold voltage less than the global power supply node voltage when the decoupling transistor is off. When the decoupling transistor(s) is/are switched on prior to word line driving operation, the voltage on the local power supply node rises to the voltage of the global power supply node. Preferably, the control signal(s) controlling the decoupling transistor(s) are, or are derived from, control signals generated for purpos…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.