Patent · US Expired

Latency time circuit for an S-DRAM

US6819624B2 · kind B2 · utility

43Cited by

4References

37Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Pramod Acharya · Munich, DE
Stefan Dietrich · Potsdam, DE
Sabine Kieser · Hausham, DE
Peter Schroegmeier · Birkenfeld, DE

Key dates

Filing date	Mar 11, 2003
Grant date	Nov 16, 2004
Priority date	—
Expiry date	Mar 11, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/0814
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.