Method and apparatus for improving the performance of a floating point multiplier accumulator
US6820106B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2000 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Mar 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position. The apparatus comprises a multiplier with a propagate, kill, generate generator (PKG generator) coupled to it. An adder, a plus-oner, a plus-two-er and a leading zero anticipator (LZA) are each coupled to the PKG generat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.