On-chip data transfer in multi-processor system
US6820143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Dec 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.