Anneal sequence for high-&kgr; film property optimization
US6821873B2 · kind B2 · utility
89Cited by
10References
22Claims
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Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Jun 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for improving high-&kgr; gate dielectric film (104) properties. The high-&kgr; film (104) is subjected to a two step anneal sequence. The first anneal is a high temperature anneal in a non-oxidizing ambient (106) such as N2 to densify the high-&kgr; film (104). The second anneal is a lower temperature anneal in an oxidizing ambient (108) to perform a mild oxidation that heals the high-&kgr; film and reduces interface defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.