Chip/package resonance damping using controlled package series resistance
US6822345B2 · kind B2 · utility
12Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Oct 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least one resistive element connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.