Read/write amplifier having vertical transistors for a DRAM memory

US6822916B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Alexander Frey · Munich, DE
• Werner Weber · Munich, DE
• Till Schlosser · Dresden, DE

Key dates

• Filing date: Jun 1, 2001
• Grant date: Nov 23, 2004
• Expiry date: Aug 17, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.