Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
US6822918B2 · kind B2 · utility
4Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2003 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Oct 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for improving speed and increasing performance in a multi-port register file memory or SRAM including at least one storage element and other circuitry that operate synchronously or asynchronously. The method comprises differentially sensing a small voltage swing in the multi-port memory using a two-stage analog-style sense amplifier including at least one trip-level-shifted inverter device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.