Method and apparatus for accounting for delays caused by logic in a network interface by integrating logic into a media access controller
US6822968B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2000 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Mar 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing link latency caused by logic in a network interface. A media access controller having a converter, modification logic, a FIFO and a controller reduces the link latency caused when the logic modifies a data packet. The converter receives frame data from a transmit buffer and converts the frame data into a data packet having a prescribed format for transmission onto a network. The logic modifies the data packet. The FIFO buffers the data packet using a plurality of flip-flops. The controller controls the flow of the data packet and determines when to transmit the data packet onto a network via a media access controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.