Data processing system having an on-chip background debug system and method therefor
US6823224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2001 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | May 13, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention relate to a mechanism to prevent the oscillator from being stopped when a host development system is coupled to the background debug communications interface and the background debug mode has been enabled. This allows background debugging operations to continue when the target data processing system is in a low power mode. Other embodiments relate to a mechanism for allowing a host development system to request a synchronization timing pulse from a target data processing system so the correct clock speed can be determined for background communications. Alternate embodiments relate to a data processing system having a system clock unit and a background debug system where the background debug system includes a background debug clock unit, separate from the system clock unit, and an enable control. When the enable control is asserted, the background debug clock unit is enabled, independent of the system clock unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.