Twin NAND device structure, array operations and fabrication method
US6825084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.