Use of fluorine implantation to form a charge balanced nitrided gate dielectric layer
US6825133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Feb 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a charge balanced, silicon dioxide layer gate insulator layer on a semiconductor substrate, with reduced leakage obtained via nitrogen treatments, has been developed. Prior to thermal growth of a silicon dioxide gate insulator layer, negatively charged fluorine ions are implanted into a top portion of a semiconductor substrate. The thermal oxidation procedure results in the growth of a silicon dioxide layer with incorporated, negatively charged fluorine ions. Subsequent nitrogen treatments, used to reduce gate insulator leakage, result in generation of positive charge in the exposed silicon dioxide layer, compensating the negatively charged fluorine ions and resulting in the desired charge balanced, silicon dioxide gate insulator layer. Nitrogen treatments can be a plasma nitridization procedure, or anneal procedure, both performed in a nitrogen containing ambient, or the positive charge can be generated in the underlying silicon dioxide gate insulator layer via deposition of an overlying silicon nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.