Input buffer for multiple differential I/O standards
US6825692B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2002 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Feb 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018585
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.