System and apparatus for reducing offset voltages in folding amplifiers
US6825716B2 · kind B2 · utility
2Cited by
4References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Apr 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/141
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and apparatus for reducing offset voltages in folding amplifiers is disclosed. In one form, a folding amplifier for use in an analog-to-digital converter is provided. The folding amplifier includes a first current source operable to be coupled to a first differential pair and a second differential pair. The folding amplifier further includes a switching network coupled between the first current source and the first and second differential pairs and operable to enable coupling the first current source to at least one of the first differential pair and the second differential pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.