Virtual ground nonvolatile semiconductor memory array architecture and integrated circuit structure therefor
US6826080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2002 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.