Low power logic gate
US6826112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Feb 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention includes a logic gate. The logic gate includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. A logic gate output is a function of charge on the charge holding device. The logic gate further includes a plurality of inputs. The plurality of inputs are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of inputs is a first voltage potential. The invention also includes an address decoder. The address decoder includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. An address decoder output is a function of charge on the charge holding device. The address decoder further includes a plurality of address lines. The plurality of address lines are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of address lines is a first voltage potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.