Optimization of die placement on wafers
US6826738B2 · kind B2 · utility
206Cited by
9References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 2, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | May 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least one effect and the user optimization data, performing optimization to determine a layout of semiconductor devices on the wafer that optimizes performance according to the user optimization data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.