Isolation chamber arrangement for serial processing of semiconductor wafers for the electronic industry
US6827789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2002 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Aug 4, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus for the treatment of semiconductor wafers, comprising a supportive frame and a process table arranged on the supportive frame. The process table comprises a stationary upper platen and a stationary lower plate. An intermediate indexing plate is rotatively arranged between the upper platen and the lower plate. At least one wafer support pin is attached to the indexing plate for the support of a wafer by the indexing plate. An upper housing is arranged on the upper platen and an outer lower housing is arranged on the lower plate. A displacable lower isolation chamber is disposed within the outer lower housing, being displacable against the indexing plate to define a treatment module between the upper housing and the lower isolation chamber in which the wafer is treated. A wafer supporting treatment plate is arranged within the lower isolation chamber, for controlled rapid treatment of a wafer within the treatment module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.