Gate pad protection structure for power semiconductor device and manufacturing method therefor

US6828177B2 · kind B2 · utility

Assignee

• Pyramis Corporation · TW

Inventors

• Jun Zeng · Torrance, US
• Ming Zhou · Torrance, US
• Tzong-Shiann Wu · Torrance, US

Key dates

• Filing date: Dec 30, 2002
• Grant date: Dec 7, 2004
• Expiry date: Dec 30, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256

Abstract

A method for manufacturing a gate pad protection structure applied in a power semiconductor device is provided. The method includes steps of (a) forming a gate oxide layer on a substrate, (b) forming a polysilicon layer on the gate oxide layer, (c) forming a polysilicon window and a polysilicon window array on the polysilicon layer, and (d) performing an ion implantation via the polysilicon window and the polysilicon window array.