Process for high voltage oxide and select gate poly for split-gate flash memory
US6828183B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2002 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Apr 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A process for forming a high voltage oxide (HV) and a select gate poly for a split-gate flash memory is disclosed. The general difficulty of forming oxides of two different thicknesses for two different areas on the same substrate is alleviated by forming an HV oxide layer over the entire substrate just prior to the forming of the control gate of a cell area after the forming of a gate oxide layer over the peripheral area of the substrate. At an immediate subsequent step, a peripheral gate is formed over the HV oxide over the peripheral area, and, as a final step, the forming of the control gate, or the select gate of the cell area follows next.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.