Sidewall polymer deposition method for forming a patterned microelectronic layer
US6828237B1 · kind B1 · utility
5Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Sep 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plasma etch method for forming a patterned target layer within a microelectrcnic product forms an etch residue layer adjoining a patterned mask layer formed upon a blanket target layer. After removing the patterned mask layer, the etch residue layer is laterally increased to form a laterally increased etch residue layer. The laterally increased etch residue layer is employed as an etch mask for forming the patterned target layer from the blanket target layer. The method is particularly useful for forming gate electrodes within semiconductor products.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.