Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
US6828635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Sep 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.