Method of forming metal fuses in CMOS processes with copper interconnect
US6828653B1 · kind B1 · utility
5Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Oct 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to at least two contacts in the metal layer. A conductive metal layer is deposited and patterned to form a fuse between the fuse contacts. A second dielectric layer is deposited on the conductive metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.