Complementary input dynamic logic for complex logic functions
US6828827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Apr 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complementary input dynamic logic circuit for evaluating a complex logic function including complementary input dynamic logic circuits, P-channel devices, an inverter/driver for providing an inverted clock signal, and N-channel pass devices. Each complementary input dynamic logic circuit determines a complementary AND function for a corresponding one of multiple sets of AND terms and indicates the complementary AND function via a corresponding one of multiple preliminary evaluation nodes. The P-channel devices are coupled in series between a source voltage and an output evaluation node. Each series-coupled P-channel device has a gate coupled to a corresponding preliminary evaluation node. The N-channel pass devices are coupled in parallel between the output evaluation node and the inverter/driver. Each N-channel pass device has a gate coupled to a corresponding preliminary evaluation node. An output driver or inverter/driver may be provided to buffer and/or invert the output evaluation node and provide a logic function result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.