Electrically erasable and programmable memory comprising an internal supply voltage management device
US6829169B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Apr 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable and programmable memory includes an array of memory cells, and a distribution line linked to a receiving terminal of an external supply voltage and to a booster circuit. The distribution line provides an internal supply voltage. The distribution line is also linked to the receiving terminal through a diode or a diode circuit simulating operation of a diode. The memory includes a regulator for triggering the booster circuit when the internal supply voltage becomes lower than a threshold so as to maintain the internal supply voltage close to the threshold when the external supply voltage is too low, at least during the reading of memory cells. The diode or the diode circuit is blocked when the external supply voltage is too low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.