Method of controlling an electronic non-volatile memory and associated device
US6829170B2 · kind B2 · utility
1Cited by
10References
35Claims
0Family size
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Key dates
| Filing date | Jul 9, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Jul 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell in an EEPROM includes a floating gate transistor that includes a first conducting terminal and a control gate. A method of controlling the memory cell includes setting a state of the memory cell by simultaneously applying voltage pulses of opposite polarities respectively to the first conducting terminal and to the control gate. The voltage pulses including a first portion having a first slope and a second portion having a second slope, wherein the second slope is based upon the polarities of the voltage pulses. The method allows the amplitude of the voltage pulses to be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.