Applications of operating mode dependent error signal generation upon real address range checking prior to translation
US6829684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2002 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Jun 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A real address range check mechanism verifies real addresses generated in a computer system which translates real addresses from effective addresses, some of the effective addresses being real addresses not requiring translation. The system has at least two operating modes. In one mode, the range checking mechanism generates an error signal responsive to detecting a real address outside a predetermined range, and in the other operating mode no error signal is generated. Preferably, the computer system's hardware resources, including real address space, is logically partitioned, partitioning being managed by an ultra-privileged process called a hypervisor. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, real address range checking error signals being disabled in the hypervisor state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.