Variable detail automatic invocation of transistor level timing for application specific integrated circuit static timing analysis
US6829755B2 · kind B2 · utility
7Cited by
9References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 16, 2001 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Aug 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for designing static timing analysis for application specific-type integrated circuits (ASIC). The method includes use of transistor level timing (TLT) methods that are used only when open channel circuit inputs are detected during the generation of the timing graph.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.