Thick traces from multiple damascene layers
US6830984B2 · kind B2 · utility
4Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2002 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Jan 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.