Memory auto-precharge
US6832286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2002 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Jul 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.