Jerome J. Johnson
30Patents
20h-index
33Co-inventors
85Inventor score
Filing activity: Sep 30, 1997 → Sep 25, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6286083A | Computer system with adaptive memory arbitration scheme | Physics | 176 | Expired |
| US6938133B2 | Memory latency and bandwidth optimizations | Physics | 116 | Expired |
| US7010652B2 | Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency | Physics | 116 | Expired |
| US6785785B2 | Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency | Physics | 114 | Expired |
| US7194577B2 | Memory latency and bandwidth optimizations | Physics | 114 | Expired |
| US6766469B2 | Hot-replace of memory | Physics | 103 | Expired |
| US6684292B2 | Memory module resync | Physics | 97 | Expired |
| US6832340B2 | Real-time hardware memory scrubbing | Physics | 64 | Expired |
| US6160562A | System and method for aligning an initial cache line of data read from local memory by an input/output device | Physics | 63 | Expired |
| US6854070B2 | Hot-upgrade/hot-add memory | Physics | 56 | Expired |
| US6202101A | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Physics | 43 | Expired |
| US5949436A | Accelerated graphics port multiple entry gart cache allocation system and method | Physics | 42 | Expired |
| US6272651A | System and method for improving processor read latency in a system employing error checking and correction | Physics | 40 | Expired |
| US6247102A | Computer system employing memory controller and bridge interface permitting concurrent operation | Physics | 40 | Expired |
| US7320086B2 | Error indication in a raid memory system | Physics | 31 | Expired |
| US6785835B2 | Raid memory | Physics | 26 | Expired |
| US6279065A | Computer system with improved memory access | Physics | 22 | Expired |
| US6356972B1 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Physics | 22 | Expired |
| US6505260B2 | Computer system with adaptive memory arbitration scheme | Physics | 20 | Expired |
| US7028213B2 | Error indication in a raid memory system | Physics | 20 | Expired |
| US6832286B2 | Memory auto-precharge | Physics | 16 | Expired |
| US6640282B2 | Hot replace power control sequence logic | Physics | 15 | Expired |
| US6209052A | System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter | Physics | 12 | Expired |
| US6199118A | System and method for aligning an initial cache line of data read from an input/output device by a central processing unit | Physics | 10 | Expired |
| US6981095B1 | Hot replace power control sequence logic | Physics | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.