Apparatus and method for providing an external clock from a circuit in sleep mode in a processor-based system
US6832327B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2001 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Mar 10, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-based system such as a workstation or server, using a system clock provided through a phase-locked loop (PLL) to a clock gate and then to a clock tree, which distributes the core system clock to components in the processor-based system, including a host bridge circuit. The host bridge distributes control signals to a receiving device such as a memory module, which may use a continued clocking signal when the system enters a low-power mode. A feedback clock for the PLL is provided to the receiving devices during low-power mode to ensure continued clocking, when the clock gate output is low and the clock tree is thereby disabled. A skew compensation circuit coordinates clocking in the continued clock and the core system clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.