Method of fabricating a stacked poly-poly and MOS capacitor using a sige integration scheme
US6833299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2002 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Nov 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
Abstract
A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.