Method and structure improving isolation between memory cell passing gate and capacitor

US6833578B1 · kind B1 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Kuo-Chi Tu · Baoshan, TW
• Chun-Yao Chen · Baoshan, TW
• Huey-Chi Chu · Taipei, TW
• Chung-Wei Chang · Baoshan, TW
• Tien-Lu Lin · Hsinchu, TW
• Kuo-Ching Huang
• Wen-Cheng Chen · Nanhu, CN
• Tsung-Hsun Huang · Taipei, TW
• Hsiao-Hui Tseng · Tainan, TW

Key dates

• Filing date: Dec 11, 2003
• Grant date: Dec 21, 2004
• Expiry date: Dec 11, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.