High voltage lateral DMOS transistor having low on-resistance and high breakdown voltage
US6833585B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2002 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Apr 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor includes a plurality of well regions of a first conductivity type formed to be spaced out within a well region of a second conductivity type between a channel region of the first conductivity type and a drain region of the second conductivity type. Most current is carried through some portions of the well region of the second conductivity type in which the well regions of the first conductivity do not appear so that the current carrying performance of the device is improved. When a bias voltage is applied to the drain region, the well region of the second conductivity type is completely depleted at other portions where the well region of the second conductivity type and the well regions of the first conductivity type alternately appear so that the breakdown voltage of the device can be increased. In addition, since the well region of the second conductivity type can be easily depleted, not only the breakdown voltage can be increased, but also the impurity concentration of the well region of the second conductivity type can be increased. Accordingly, the on-resistance of the device can be decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.