Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
US6834328B2 · kind B2 · utility
7Cited by
9References
12Claims
0Family size
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Key dates
| Filing date | Jan 27, 2004 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Jan 27, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.