Method of testing embedded memory array and embedded memory controller for use therewith
US6834361B2 · kind B2 · utility
24Cited by
13References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Feb 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test controller comprises a test instruction register array for storing a plurality of test instructions, each register having instruction fields for storing instruction data specifying operations to be performed on the memory array, a repeat module for repeating a group of one or more of the test instructions with modified data, the repeat module including storage means for storing instruction field modification data; and each register of the test instruction register array including an instruction field for enabling or disabling the repeat module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.