Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package
US6835595B1 · kind B1 · utility
37Cited by
5References
8Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 4, 2001 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Apr 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.