Patent · US Expired

Method for fabricating a MOSFET having a very small channel length

US6835612B2 · kind B2 · utility

4Cited by

4References

13Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Annalisa Cappellani · Portland, US
Ludwig Dittmar · Dresden, DE
Dirk Schumann · Lübbenau/Spreewald - Lubnjow/Błota, DE

Key dates

Filing date	Sep 26, 2003
Grant date	Dec 28, 2004
Priority date	—
Expiry date	Sep 26, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/0223
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length to form a dimensionally accurate T-gate transistor with a very short channel length.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.