NMOS ESD protection device with thin silicide and methods for making same
US6835623B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2003 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Feb 24, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/70
Abstract
An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.