ESD/EOS protection structure for integrated circuit devices and methods of fabricating the same
US6835650B1 · kind B1 · utility
4Cited by
44References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2000 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Nov 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
Apparatus and methods forming electrostatic discharge and electrical overstress protection devices for integrated circuits wherein such devices include shared electrical contact between source regions and between drain regions for more efficient dissipation of an electrostatic discharge. The devices further include contact plugs and contact lands which render the fabrication of the devices less sensitive to alignment constraint in the formation of contacts for the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.